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SI8410/20/21
SINGLE & D U A L - C H A N N E L D I G I TA L I S O L A T O R S
Features
High-speed operation
DC - 150 Mbps
2500 VRMS isolation Transient Immunity
>25 kV/s
Pin Assignments
Low propagation delay
<10 ns
Narrow Body SOIC
Si841x
VDD1 A1 VDD1 GND1
Wide Operating Supply Voltage: 2.375-5.5 V Low power
I1 + I2 < 12 mA/channel at 100 Mbps
DC correct No start-up initialization required <10 s Startup Time High temperature operation
125 C at 100 Mbps 100 C at 150 Mbps
Precise timing
2 ns pulse width distortion 1 ns channel-channel matching 2 ns pulse width skew
1 2 3 4
Top View
8 7 6 5
VDD2 GND2 B1 GND2
Narrow body SOIC-8 package
Si842x
VDD1 A1
Applications
Isolated switch mode supplies Isolated ADC, DAC Motor control Power factor correction systems
A2 GND1
1 2 3 4
Top View
8 7 6 5
VDD2 B1 B2 GND2
Safety Regulatory Approvals
UL recognition:2500 Vrms for 1 Minute per UL1577 CSA component acceptance notice IEC certification conformity
IEC 60747-5-2 (VDE0884 Part 2)
Description
The Silicon Laboratories family of digital isolators are CMOS devices that employ an RF coupler to transmit digital information across an isolation barrier. Very high speed operation at low power levels is achieved. These parts are available in an 8-pin narrow-body SOIC package. Three speed grade options (1, 10, and 150 Mbps) are available and achieve typical propagation delays of less than 10 ns.
Block Diagram
SI8410 Si8420 Si8421
A1
B1
A1 A2
B1 B2
A1 A2
B1 B2
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Preliminary Rev. 0.1 5/07
Copyright (c) 2007 by Silicon Laboratories
SI8410/20/21
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SI8410/20/21
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SI8410/20/21 TABLE O F CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . . 22 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7. Package Outline: 8-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
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1. Electrical Specifications
Table 1. Electrical Characteristics
(VDD1 = 5 V, VDD2 = 5 V, TA = -40 to 125 C)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current SI8410-A,-B,-C, VDD1 SI8410-A,-B,-C, VDD2 SI8410-A,-B,-C, VDD1 SI8410-A,-B,-C, VDD2 Si8420-A,-B,-C, VDD1 Si8420-A,-B,-C, VDD2 Si8420-A,-B,-C, VDD1 Si8420-A,-B,-C, VDD2 Si8421-A,-B,-C, VDD1 Si8421-A,-B,-C, VDD2 Si8421-A,-B,-C, VDD1 Si8421-A,-B,-C, VDD2 SI8410-B,-C, VDD1 SI8410-B,-C, VDD2 Si8420-B,-C, VDD1 Si8420-B,-C, VDD2 Si8421-B,-C, VDD1 Si8421-B,-C, VDD2 SI8410-C, VDD1 SI8410-C, VDD2 Si8420-C, VDD1 Si8420-C, VDD2 Si8421-C, VDD1 Si8421-C, VDD2
Symbol VIH VIL VOH VOL IL
Test Condition
Min 2.0 --
Typ -- -- 4.8 0.2 -- 7 3 9 3 7 4 11 4 9 9 10 10 8 5 9 9 12 12 8 15 9 30 21 21
Max -- 0.8 -- 0.4 10 10 5 14 5 10 7 15 6 12 12 14 14 12 7 13 12 16 16 12 22 13 39 27 27
Unit V V V V A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
loh = -4 mA lol = 4 mA
VDD1,VDD2 - 0.4 -- --
DC Supply Current (All inputs 0 V or at Supply) All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
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Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V, VDD2 = 5 V, TA = -40 to 125 C)
Parameter
Symbol
Test Condition Timing Characteristics Si841x/2x-A
Min
Typ
Max
Unit
Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 1 See Figure 1
0 -- 25 -- -- -- 0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 1 See Figure 1 10 -- -- -- 0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 1 See Figure 1 4 -- -- --
-- -- 40 -- -- -- -- -- 20 -- -- -- -- -- 6.5 -- -- --
1 1000 75 30 50 40 10 100 35 7.5 25 5 150 6.6 9.5 3.5 5.5 3
Mbps ns ns ns ns ns Mbps ns ns ns ns ns Mbps ns ns ns ns ns
Propagation Delay Skew1
Channel-Channel Skew Si841x/2x-B Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL|
Propagation Delay Skew1
Channel-Channel Skew Si841x/2x-C Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL|
Propagation Delay Skew1
Channel-Channel Skew
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Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V, VDD2 = 5 V, TA = -40 to 125 C)
Parameter Output Rise Time Output Fall Time Common Mode Transient Immunity Start-up Time2
Symbol tr tf CTMI tSU
Test Condition For All Models CL = 15 pF CL = 15 pF VI = VDD or 0 V
Min -- -- 25 --
Typ 2 2 30 3
Max -- -- -- --
Unit ns ns kV/s s
Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output.
50% Typical Input
tPLH
90% 50% 90% 10%
tPHL
Typical Output
10%
tr
tf
Figure 1. Propagation Delay Timing
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Table 2. Electrical Characteristics
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = -40 to 125 C)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current SI8410-A,-B,-C, VDD1 SI8410-A,-B,-C, VDD2 SI8410-A,-B,-C, VDD1 SI8410-A,-B,-C, VDD2 Si8420-A,-B,-C, VDD1 Si8420-A,-B,-C, VDD2 Si8420-A,-B,-C, VDD1 Si8420-A,-B,-C, VDD2 Si8421-A,-B,-C, VDD1 Si8421-A,-B,-C, VDD2 Si8421-A,-B,-C, VDD1 Si8421-A,-B,-C, VDD2 SI8410-B,-C, VDD1 SI8410-B,-C, VDD2 Si8420-B,-C, VDD1 Si8420-B,-C, VDD2 Si8421-B,-C, VDD1 Si8421-B,-C, VDD2 SI8410-C, VDD1 SI8410-C, VDD2 Si8420-C, VDD1 Si8420-C, VDD2 Si8421-C, VDD1 Si8421-C, VDD2 www..com
Symbol VIH VIL VOH VOL IL
Test Condition
Min 2.0 --
Typ -- -- 3.1 0.2 -- 6 2 8 2 7 4 10 4 8 8 9 9 7 4 8 8 10 10 7 10 8 20 17 17
Max -- 0.8 -- 0.4 10 9 4 13 4 9 6 14 6 11 11 13 13 11 6 12 12 14 14 11 16 12 26 21 21
Unit V V V V A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
loh = -4 mA lol = 4 mA
VDD1,VDD2 - 0.4 -- --
DC Supply Current (All inputs 0 V or at supply) All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
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Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = -40 to 125 C)
Parameter Si841x/2x-A Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si841x/2x-B Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Si841x/2x-C Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics 0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 1 See Figure 1 25 -- -- -- 0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 1 See Figure 1 10 -- -- -- 0 -- tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 1 See Figure 1 4 -- -- -- -- -- 40 -- -- -- -- -- 20 -- -- -- -- -- 7.5 -- -- -- 1 1000 75 30 50 40 10 100 35 7.5 25 5 150 6.6 10 3.5 5.5 3 Mbps ns ns ns ns ns Mbps ns ns ns ns ns Mbps ns ns ns ns ns
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Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = -40 to 125 C)
Parameter Output Rise Time Output Fall Time Common Mode Transient Immunity Start-up Time2
Symbol tr tf CTMI tSU
Test Condition For All Models CL = 15 pF CL = 15 pF VI = VDD or 0 V
Min -- -- 25 --
Typ 2 2 30 3
Max -- -- -- --
Unit ns ns kV/s s
Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output.
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Table 3. Electrical Characteristics
(VDD1 = 2.5 V, VDD2 = 2.5 V, TA = -40 to 100 C)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current SI8410-A,-B,-C, VDD1 SI8410-A,-B,-C, VDD2 SI8410-A,-B,-C, VDD1 SI8410-A,-B,-C, VDD2 Si8420-A,-B,-C, VDD1 Si8420-A,-B,-C, VDD2 Si8420-A,-B,-C, VDD1 Si8420-A,-B,-C, VDD2 Si8421-A,-B,-C, VDD1 Si8421-A,-B,-C, VDD2 Si8421-A,-B,-C, VDD1 Si8421-A,-B,-C, VDD2 SI8410-B,-C, VDD1 SI8410-B,-C, VDD2 Si8420-B,-C, VDD1 Si8420-B,-C, VDD2 Si8421-B,-C, VDD1 Si8421-B,-C, VDD2 SI8410-C, VDD1 SI8410-C, VDD2 Si8420-C, VDD1 Si8420-C, VDD2 Si8421-C, VDD1 Si8421-C, VDD2
Symbol VIH VIL VOH VOL IL
Test Condition
Min 2.0 --
Typ -- -- 2.3 0.2 -- 5 2 7 2 6 4 9 3 7 7 8 8 6 3 7 6 8 8 6 7 7 12 12 12
Max -- 0.8 -- 0.4 10 7 3 9 3 7 5 11 5 9 9 10 10 8 5 9 8 11 11 8 10 9 15 15 15
Unit V V V V A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
loh = -4 mA lol = 4 mA
VDD1,VDD2 - 0.4 -- --
DC Supply Current (All inputs 0 V or at supply) All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
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Table 3. Electrical Characteristics (Continued)
(VDD1 = 2.5 V, VDD2 = 2.5 V, TA = -40 to 100 C)
Parameter
Symbol
Test Condition Timing Characteristics Si841x/2x-A
Min
Typ
Max
Unit
Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew1 Channel-Channel Skew tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 1 See Figure 1 tPHL, tPLH PWD tPSK(P-P) tPSK Si841x/2x-C See Figure 1 See Figure 1 tPHL, tPLH PWD tPSK(P-P) tPSK Si841x/2x-B See Figure 1 See Figure 1
0 -- 25 -- -- -- 0 -- 10 -- -- -- 0 -- 5 -- -- --
-- -- 40 -- -- -- -- -- 20 -- -- -- -- -- 10 -- -- --
1 1000 75 30 50 40 10 100 35 7.5 25 5 100 10 17 7 12 4
Mbps ns ns ns ns ns Mbps ns ns ns ns ns Mbps ns ns ns ns ns
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Table 3. Electrical Characteristics (Continued)
(VDD1 = 2.5 V, VDD2 = 2.5 V, TA = -40 to 100 C)
Parameter Output Rise Time Output Fall Time Common Mode Transient Immunity Start-up Time2
Symbol tr tf CTMI tSU
Test Condition For All Models CL = 15 pF CL = 15 pF VI = VDD or 0 V
Min -- -- 25 --
Typ 2 2 30 3
Max -- -- -- --
Unit ns ns kV/s s
Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output.
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Table 4. Absolute Maximum Ratings
Parameter Storage Temperature Operating Temperature Supply Voltage Input Voltage Output Voltage Output Current Drive Channel Lead Solder Temperature (10s) Maximum Isolation Voltage Symbol TSTG TA VDD1, VDD2 VI VO LO Min -65 -40 -0.5 -0.5 -0.5 -- -- -- Typ -- -- -- -- -- -- -- -- Max 150 125 6 VDD + 0.5 VDD + 0.5 10 260 4000 Unit C C V V V mA C VDC
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet.
Table 5. Recommended Operating Conditions
Parameter Ambient Operating Temperature* Supply Voltage Symbol TA VDD1 VDD2 Test Condition 100 Mbps, 15 pF, 5 V 150 Mbps, 15 pF, 5 V Min -40 0 2.375 2.375 Typ 25 25 -- -- Max 125 100 5.5 5.5 Unit C C V V
*Note: The maximum ambient temperature is dependent upon data frequency, output loading, the number of operating channels, and supply voltage.
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Table 6. Regulatory Information
CSA The Si84xx is certified under CSA Component Acceptance Notice. For more details, see File 232873. VDE The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. UL The Si84xx is certified under UL1577 component recognition program to provide basic insulation to 2500 VRMS (1 minute). It is production tested > 3000 VRMS for 1 second. For more details, see File E257455.
Table 7. Insulation and Safety-related Specifications
Parameter Minimum Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Resistance (Input-Output)1 Capacitance (Input-Output) Input Capacitance2
1
Symbol L(IO1) L(IO2)
Test Condition
Value 5.0 min 4.60 0.008 min
Unit mm mm mm V pF pF
CTI RIO CIO CI
DIN IEC 60112/VDE 0303 Part 1
>175 1012
f = 1 MHz
1.4 4.0
Notes: 1. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1-4 are shorted together to form the first terminal and pins 5-8 are shorted together to form the second terminal. The parameters are then measured between these two terminals. 2. Measured from input pin to ground.
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Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter Basic isolation group Test Conditions Material Group Rated Mains Voltages < 150 VRMS Installation Classification Rated Mains Voltages < 300 VRMS Rated Mains Voltages < 400 VRMS Specification IIIa I-IV I-III I-II
Table 9. IEC 60747-5-2 Insulation Characteristics*
Parameter Maximum Working Insulation Voltage Symbol VIORM Method a After Environmental Tests Subgroup 1 (VIORM x 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC) Input to Output Test Voltage VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) After Input and/or Safety Test Subgroup 2/3 (VIORM x 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC) Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V RS VTR Test Condition Characteristic 560 Unit V peak
896
1050
V peak
672 4000 2 >109 V peak
*Note: The Si84xx is suitable for basic electrical isolation a climate classification of 40/125/21.
Table 10. IEC Safety Limiting Values
Parameter Case Temperature Safety input, output, or supply current Symbol TS IS JA = 210 C/W, VI = 5.5 V, TJ = 150 C, TA = 25 C Test Condition Min -- -- Typ
--
Max 150 105
Unit C mA
--
*Note: Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 2.
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Table 11. Thermal Characteristics
Parameter IC Junction-to-Case Thermal Resistance Symbol JC Test Condition Thermocouple located at center of package Min -- Typ 100 Max -- Unit C/W
IC Junction-to-Air Thermal Resistance Device Power Dissipation*
JA PD
-- --
210 --
-- 250
C/W mW
*Note: The Si8420-C-IS is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 C, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
Safety-Limiting Current (mA)
100 75 50 25 0 0 50 100 150 Case Temperature (C) 200
78 5.5 V 3.6 V
121 128 106
2.75 V
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2
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2. Typical Performance Characteristics
10 9 Current (mA)
Current (mA) 20 5V
5V 8 3.3V 7 6 5 0 10 20 30 40 50 60 70 80 90 100 Data Rate (Mbps) 2.5V
15 10
3.3V 2.5V
5 0 0 10 20 30 40 50 60 70 80 90 100 Data Rate (Mbps)
Figure 3. SI8410 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation
12 10 Current (mA) 8 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 Data Rate (Mbps) 2.5V 5V 3.3V
Figure 6. Si8420 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load)
19 17 Current (mA) 15 13 11 9 7 5 0 10 20 30 40 50 60 70
5V 3.3V 2.5V
80
90
100
Data Rate (Mbps)
Figure 4. SI8410 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load)
Figure 7. Si8421 Typical VDD1 or VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load)
15 13 Current (mA) 11 9 7 5 0 10 20 30 40 50 60 70 80 90 100 Data Rate (Mbps) 5V 3.3V 2.5V
Figure 5. Si8420 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation
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10 9 Delay (ns) 8 Falling Edge 7 6 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Rising Edge
Figure 8. Propagation Delay vs. Temperature 5 V Operation
10 9 Delay (ns) 8 7 6 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Falling Edge Rising Edge
Figure 9. Propagation Delay vs. Temperature 3.3 V Operation
15 13 Delay (ns) 11 9 7 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Falling Edge Rising Edge
Figure 10. Propagation Delay vs. Temperature 2.5 V Operation
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3. Application Information
3.1. Theory of Operation
The operation of an Si841x or Si842x channel is analogous to that of an opto coupler, except that an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at startup. A simplified block diagram for a single SI8410 channel is shown in Figure 11. A channel consists of an RF transmitter and receiver separated by a transformer. Referring to the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying and applies the resulting waveform to the primary of the transformer. The receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver.
TRANSMITTER
RF OSCILLATOR
RECEIVER
A
MODULATOR
DEMODULATOR
B
Figure 11. Simplified Channel Diagram
3.2. Eye Diagram
Figure 12 illustrates an eye-diagram taken on an SI8410. The test used an Anritsu (MP1763C) Pulse Pattern Generator for the data source. The output of the generator's clock and data from an SI8410 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that very low pulse width distortion and very little jitter were exhibited.
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Figure 12. Eye Diagram
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4. Layout Recommendations
Dielectric isolation is a set of specifications produced by safety regulatory agencies from around the world, which describes the physical construction of electrical equipment that derives power from high-voltage power systems, such as 100-240 VAC systems or industrial power. The dielectric test (or HIPOT test) given in the safety specifications places a very high voltage between the input power pins of a product and the user circuits and the user-touchable surfaces of the product. For the IEC relating to products deriving their power from the 220-240 V power grids, the test voltage is 2500 VAC (or 3750 VDC, the peak equivalent voltage). There are two terms described in the safety specifications: Creepage--the distance along the insulating surface an arc may travel. Clearance--the shortest distance through air that an arc may travel. Figure 13 illustrates the accepted method of providing the proper creepage distance along the surface. For a 220-240 V application, this distance is 8 mm, and the wide-body SOIC package must be used. There must be no copper traces within this 8 mm exclusion area, and the surface should have a conformal coating, such as solder resist. The digital isolator chip must straddle this exclusion area.
Figure 13. Creepage Distance
4.1. Supply Bypass
The Si841x and Si842x families require a 0.1 F bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed as close as possible to the package.
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4.2. Input and Output Characteristics
The Si841x and Si842x inputs and outputs are standard CMOS drivers/receivers. Table 12 details powered and unpowered operation of the Si84xx.
Table 12. Si84xx Operation Table
VI Input1,4 VDDI State1,2,3 VDDO State1,2,3 VO Output1,4 H L X P P UP P P P H L L Normal operation. Upon the transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 s. Upon the transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 s. Comments
X
P
UP
L
Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. 2. Powered (P) state is defined as 2.375 V < VDD < 5.5 V. 3. Unpowered (UP) state is defined as VDD = 0 V. 4. X = not applicable; H = Logic High; L = Logic Low.
4.3. RF Radiated Emissions
The Si841x and Si842x families use an RF carrier frequency of approximately 2.1 GHz. This will result in a small amount of radiated emissions at this frequency and its harmonics. The radiation is not from the IC chip but, rather, is due to a small amount of RF energy driving the isolated ground planes, which can act as a dipole antenna. The unshielded SI8410 evaluation board passes FCC requirements. Table 13 shows measured emissions compared to FCC requirements. Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less efficient antenna.
Table 13. Radiated Emissions
Frequency Measured (GHz) (dBV/m) 2.094 2.168 4.210 4.337 6.315 6.505 8.672 70.0 68.3 61.9 60.7 58.3 60.7 45.6 FCC Spec (dBV/m) 74.0 74.0 74.0 74.0 74.0 74.0 74.0 Compared to Spec (dB) -4.0 -5.7 -12.1 -13.3 -15.7 -13.3 -28.4
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4.4. RF Immunity and Common Mode Transient Immunity
The Si841x and Si842x families have very high common mode transient immunity while transmitting data. This is typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds. Measurements show no failures up to 30 kV/s. During a high surge event, the output may glitch low for up to 20-30 ns, but the output corrects immediately after the surge event. The Si841x and Si842x families pass the industrial requirements of CISPR24 for RF immunity of 3 V/m using an unshielded evaluation board. As shown in Figure 14, the isolated ground planes form a parasitic dipole antenna, while Figure 15 shows the RMS common mode voltage versus frequency above which the Si841x becomes susceptible to data corruption. To avoid compromising data, care must be taken to keep RF common-mode voltage below the envelope specified in Figure 15. The PCB should be laid-out to not act as an efficient antenna for the RF frequency of interest. RF susceptibility is also significantly reduced when the end system is housed in a metal enclosure, or otherwise shielded.
GND1
Isolator
GND2
Dipole Antenna
Figure 14. Dipole Antenna
5 RMS Voltage (V) 4 3 2 1 0 500
1000 Frequency (MHz)
1500
2000
Figure 15. RMS Common Mode Voltage vs. Frequency
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5. Pin Descriptions
Si841x
VDD1 A1 VDD1 GND1
Si842x
1 2 3 4
Top View
8 7 6 5
VDD2 GND2 B1 GND2
VDD1 A1 A2 GND1
1 2 3 4
Top View
8 7 6 5
VDD2 B1 B2 GND2
Narrow Body SOIC
Name VDD1 GND1 A1 A2 B1 B2 VDD2 GND2 SOIC-8 Pin# SI8410 1,3 4 2 NA 6 NA 8 5,7 SOIC-8 Pin# Si8420/21 1 4 2 3 7 6 8 5 Type Supply Ground Digital I/O Digital I/O Digital I/O Digital I/O Supply Ground Description Side 1 power supply. Side 1 ground. Side 1 digital input or output. Side 1 digital input or output. Side 2 digital input or output. Side 2 digital input or output. Side 2 power supply. Side 2 ground.
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6. Ordering Guide
Ordering Part Number SI8410-A-IS SI8410-B-IS SI8410-C-IS Si8420-A-IS Si8420-B-IS Si8420-C-IS Si8421-A-IS Si8421-B-IS Si8421-C-IS Number of Inputs Number of Inputs VDD1 Side VDD2 Side 1 1 1 2 2 2 1 1 1 0 0 0 0 0 0 1 1 1 Maximum Data Rate 1 10 150 1 10 150 1 10 150 Temperature -40 to 125 C -40 to 125 C -40 to 125 C -40 to 125 C -40 to 125 C -40 to 125 C -40 to 125 C -40 to 125 C -40 to 125 C Package Type SOIC-8 SOIC-8 SOIC-8 SOIC-8 SOIC-8 SOIC-8 SOIC-8 SOIC-8 SOIC-8
Note: All packages are Pb-free and RoHS Compliant. Moisture sensitivity level is MSL2 with peak reflow temperature of 260 C according to the JEDEC industry standard classifications and peak solder temperature.
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7. Package Outline: 8-Pin SOIC
Figure 16 illustrates the package details for the Si84xx. Table 14 lists the values for the dimensions shown in the illustration.
Figure 16. 8-pin Small Outline Integrated Circuit (SOIC) Package Table 14. Package Diagram Dimensions
Symbol A A1 A2 B C D E e H h L
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Millimeters Min 1.35 0.10 1.40 REF 0.33 0.19 4.80 3.80 5.80 0.25 0.40 0 Max 1.75 0.25 1.55 REF 0.51 0.25 5.00 4.00 6.20 0.50 1.27 8
1.27 BSC
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CONTACT INFORMATION
Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: PowerProducts@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. www..com Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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